1. Technical Field
The present invention relates to an electrical laminate structure, and associated method of formation, having multilevel conductive vias that are electrically coupled to circuit features of the electrical laminate structure.
2. Related Art
A capability for increasing the yield of fabricated printed circuit structures would lower costs and improve profitability. Additionally, providing additional ways of electrically coupling circuit features of a printed circuit structure would improve design flexibility and efficiency.
Accordingly, there is a need for increasing the yield of fabricated printed circuit structures. Additionally, there is a need for providing additional ways of electrically coupling circuit features of a printed circuit structure.
The present invention provides a method of forming an electrical structure, comprising:
forming a complex power-signal (CPS) substructure;
testing an electrical performance of the CPS substructure to determine whether the CPS substructure satisfies electrical performance acceptance requirements, wherein the testing includes testing for at least one of electrical integrity and electrical signal delay, and wherein the testing for electrical integrity includes testing for at least one of an electrical short, an electrical open, and an erroneous impedance; and
if the testing determines that the CPS substructure satisfies the electrical performance acceptance requirements, then forming a dielectric-metallic (DM) laminate on a first external surface of the CPS substructure including forming a first multilevel conductive via through the DM laminate, wherein the DM laminate includes an alternating sequence of an equal number N of dielectric layers and metallic layers such that a first dielectric layer of the N dielectric layers is formed on the first external surface of the CPS substructure, wherein N is at least 2, and wherein the multilevel conductive via is electrically coupled to a first metal layer of the CPS substructure.
The present invention provides an electrical structure, comprising:
a complex power-signal (CPS) substructure;
a dielectric-metallic (DM) laminate that includes an alternating sequence of an equal number N of dielectric layers and metallic layers such that a first dielectric layer of the N dielectric layers is formed on a first external surface of the CPS substructure, wherein N is at least 2; and
a first multilevel conductive via through the DM laminate, wherein the first multilevel conductive via is electrically coupled to a first metal layer of the CPS substructure.
The present invention provides an electrical structure, comprising:
a complex power-signal (CPS) substructure that has passed an electrical performance acceptance test for at least one of an electrical integrity and electrical signal delay, wherein the test for electrical integrity includes a test for at least one of an electrical short, an electrical open, and an erroneous impedance;
a dielectric-metallic (DM) laminate that includes an alternating sequence of an equal number N of dielectric layers and metallic layers such that a first dielectric layer of the N dielectric layers is formed on a first external surface of the CPS substructure, wherein N is at least 2; and
a first multilevel conductive via through the DM laminate, wherein the first multilevel conductive via is electrically coupled to a first metal layer of the CPS substructure.
The present invention facilitates increasing the yield of fabricated electrical laminate structures (e.g., printed circuit structures). Additionally, the present invention provides additional ways of electrically coupling circuit features of an electrical laminate structure.